@conference {wei2003500mhz,
	title = {A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS},
	booktitle = {2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
	year = {2003},
	pages = {464{\textendash}465},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Low-jitter clock generation is a critical component for enabling robust high-speed operation of 5Gb/s backplane transceivers. The implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying delay-locked loop (MDLL) is described. The choice depends on the noise characteristics of the input clock source. This MP/DLL design is implemented in a 0.25/spl mu/m CMOS process and operates with a 2.5V supply.},
	url = {https://doi.org/10.1109/ISSCC.2003.1234388},
	author = {Gu  Wei and Stonick T and Weinlader Dan and Sonntag Jeff and Searles Shawn}
}
