@conference {chung20097,
	title = {A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS},
	booktitle = {2009 Symposium on VLSI Circuits},
	year = {2009},
	pages = {268{\textendash}269},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Kyoto, Japan},
	abstract = {<p>
	A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low power consumption. The 7.5-GS/s flash ADC consumes 52-mW and occupies 0.01-mm\&nbsp;<sup>2</sup>\&nbsp;. Clock duty cycle control improves ENOB from 3.5 to 3.8 with an input sinusoid at the Nyquist frequency.
</p>
},
	url = {https://ieeexplore.ieee.org/abstract/document/5205316/similar$\#$similar},
	author = {Chung, Hayun and Rylyakov, Alexander and Deniz, Toprak and Bulzacchelli, John and Gu  Wei and Friedman Daniel}
}
