@conference {reddi2010voltage,
	title = {Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling},
	booktitle = {2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture},
	year = {2010},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-threaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4\%, far from the processor{\textquoteright}s 14\% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today{\textquoteright}s processors, such resilient designs could yield 15\% to 20\% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.},
	keywords = {voltage-noise},
	url = {https://doi.org/10.1109/MICRO.2010.35},
	author = {Vijay Reddi and Svilen Kanev and Wonyoung Kim and Simone Campanoni and Michael  Smith and Gu  Wei and David Brooks}
}
