@conference {Shao2015_scaw,
	title = {Toward Cache-Friendly Hardware Accelerators},
	booktitle = {HPCA Sensors and Cloud Architectures Workshop (SCAW)},
	year = {2015},
	abstract = {Increasing demand for power-efficient, high-performance computing has spurred a growing number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as servers and desktops. Despite their energy efficiency, fixed-function accelerators lack programmability, especially compared with general-purpose processors. Today{\textquoteright}s accelerators rely on software-managed scratchpad memory and Direct Memory Access (DMA) to provide fixed-latency memory access and data transfer, which leads to significant chip resource and software engineering costs. On the other hand, hardware-managed caches with support for virtual memory and cache coherence are well-known to ease programmability in general-purpose processors, but these features are not commonly supported in today{\textquoteright}s fixed-function accelerators. As a first step toward cache-friendly accelerator design, this paper discusses limitations of scratchpad-based memories in today{\textquoteright}s accelerators, identifies challenges to support hardware-managed caches, and explores opportunities to ease the cache integration.},
	keywords = {accelerators, aladdin},
	url = {http://www.eecs.harvard.edu/~shao/papers/shao2015-scaw.pdf},
	author = {Yakun Shao and Sam Xi and Viji Srinivasan and Gu  Wei and David Brooks}
}
