@conference {Reagen2016,
	title = {Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators},
	booktitle = {International Symposium on Computer Architecture (ISCA)},
	year = {2016},
	address = {Seoul, Korea (South)},
	abstract = {The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous datatype optimization reduces power by 1.5{\texttimes}; aggressive, inline predication and pruning of small activity values further reduces power by 2.0{\texttimes}; and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7{\texttimes} through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1{\texttimes} power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.},
	keywords = {accelerators, dnn, machine learning, power},
	url = {https://doi.org/10.1109/ISCA.2016.32},
	author = {Brandon Reagen and Paul Whatmough and Robert Adolf and Saketh Rama and Hyunkwang Lee and Sae Kyu Lee and Jos{\'e} Hern{\'a}ndez-Lobato and Gu  Wei and David Brooks}
}
