@article {Whatmough2018b,
	title = {SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devices},
	journal = {Hot Chips 30: A Symposium on High Performance Chips},
	volume = {99},
	year = {2018},
	pages = {1-1},
	abstract = {Emerging Internet of Things (IoT) devices necessitate system-on-chips (SoCs) that can scale from ultralow power always-on (AON) operation, all the way up to less frequent high-performance tasks at high energy efficiency. Specialized accelerators are essential to help meet these needs at both ends of the scale, but maintaining workload flexibility remains an important goal. This article presents a 25-mm{\texttwosuperior} SoC in 16-nm FinFET technology which demonstrates targeted, flexible acceleration of key compute-intensive kernels spanning machine learning (ML), DSP, and cryptography. The SMIV SoC includes a dedicated AON sub-system, a dual-core Arm Cortex-A53 CPU cluster, an SoC-attached embedded field-programmable gate array (eFPGA) array, and a quad-core cache-coherent accelerator (CCA) cluster. Measurement results demonstrate: 1) 1236x power envelope, from 1.1 mW (only AON cluster), up to 1.36 W (whole SoC at maximum throughput); 2) 5.5-28.9x energy efficiency gain from offloading compute kernels from A53 to eFPGA; 3) 2.94x latency improvement using coherent memory access (CCA cluster); and 4) 55x MobileNetV1 energy per inference improvement on CCA compared to the CPU baseline. The overall flexibility-efficiency range on SMIV spans measured energy efficiencies of 1x (dual-core A53), 3.1x (A53 with SIMD), 16.5x (eFPGA), 54.9x (CCA), and 256x (AON) at a peak efficiency of 4.8 TOPS/W.},
	keywords = {accelerators, deep learning},
	url = {http://dx.doi.org/10.1109/JSSC.2021.3115466},
	author = {Paul Whatmough and Sae Lee and Sam Xi and Udit Gupta and Lillian Pentecost and Marco Donato and Hsea Hseuh and David Brooks and Gu  Wei}
}
