@article {Lee2018,
	title = {A wide dynamic range sparse FC-DNN processor with multi-cycle banked SRAM read and adaptive clocking in 16nm FinFET},
	journal = {ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference},
	year = {2018},
	abstract = {Always-on classifiers for sensor data require a very wide operating range to support a variety of real-time workloads and must operate robustly at low supply voltages. We present a 16nm always-on wake-up controller with a fully-connected (FC) Deep Neural Network (DNN) accelerator that operates from 0.4-1 V. Calibration-free automatic voltage/frequency tuning is provided by tracking small non-zero Razor timing-error rates, and a novel timing-error driven sync-free fast adaptive clocking scheme provides resilience to on-chip supply voltage noise. The model access burden of neural networks is relaxed using a multicycle SRAM read, which allows memory voltage to be reduced at iso-throughput. The wide operating range allows for high performance at 1.36GHz, low-power consumption down to 750μW and state-of-the-art raw efficiency at 16-bit precision of 750 GOPS/W dense, or 1.81 TOPS/W sparse.},
	keywords = {accelerators, deep learning},
	url = {https://ieeexplore.ieee.org/abstract/document/8494245},
	author = {Sae Lee and Paul Whatmough and Niamh Mulholland and Patrick Hansen and David Brooks and Gu  Wei}
}
