@article {Whatmough2019,
	title = {A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators},
	journal = {Symposium on VLSI Circuits},
	year = {2019},
	abstract = {This paper presents a 25mm^2 SoC in 16nm FinFET technology targeting flexible acceleration of compute intensive kernels in DNN, DSP and security algorithms. The SoC includes an always-on sub-system, a dual-core Arm A53 CPU cluster, an embedded FPGA array, and a quad-core cache-coherent accelerator cluster. Measurement results demonstrate the following observations: 1) moving DSP/cryptography kernels from A53 to eFPGA increases energy efficiency between 5.5{\texttimes} - 28.9{\texttimes}, 2) the use of cache coherency for datapath accelerators increases throughput by 2.94{\texttimes}, and 3) accelerator flexibility-efficiency (GOPS/W) range spans from 3.1{\texttimes} (A53+S1MD), to 16.5{\texttimes} (eFPGA), to 54.5{\texttimes} (CCA) compared to the dual-core CPU baseline on comparable tasks. The energy per inference on MobileNet-128 CNN shows a peak improvement of 47.6{\texttimes}.},
	keywords = {deep learning, hardware support for machine learning, machine learning, neural network accelerators},
	url = {https://ieeexplore.ieee.org/abstract/document/8778002/authors$\#$authors},
	author = {Paul Whatmough and Sae Lee and Marco Donato and Hsea Hsueh and Sam Xi and Udit Gupta and Lillian Pentecost and Ko, Glenn and David Brooks and Gu  Wei}
}
