A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders


Ratnayake NS, Haratsch F, and Gu Wei. 12/2007. “A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders.” In IEEE GLOBECOM 2007-IEEE Global Telecommunications Conference, Pp. 265–270. IEEE. Publisher's Version


A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.
Last updated on 05/02/2022