A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction

Citation:

Ankur Agrawal, Pavan Kumar Hanumolu, and Gu-Yeon Wei. 9/21/2008. “A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction.” In 2008 IEEE Custom Integrated Circuits Conference, Pp. 459–462. IEEE. Publisher's Version

Abstract:

This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.
Last updated on 04/29/2022