An 8$, times, $5 Gb/s Parallel Receiver With Collaborative Timing Recovery


Ankur Agrawal, Andrew Liu, Pavan Kumar Hanumolu, and Gu-Yeon Wei. 8/2009. “An 8$, times, $5 Gb/s Parallel Receiver With Collaborative Timing Recovery.” IEEE Journal of Solid-State Circuits, 44, 11, Pp. 3120–3130. Publisher's Version


This paper presents the design of an 8 channel, 5 & Gb/s per channel parallel receiver with collaborative timing recovery and no forwarded clock. The receiver architecture exploits synchrony in the transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. This collaborative timing recovery scheme enables wideband jitter tracking without increasing the dithering jitter in the synthesized clock. Circuit design techniques employed to implement this receiver architecture are discussed. Experimental results from a 130 nm CMOS test chip demonstrate the enhanced tracking bandwidth and lower dithering jitter of the recovered clock.
Last updated on 04/28/2022