# eNVM ## expand\_more ## Emerging Embedded Non-Volatile Memory (eNVM) Technologies ![envm_fig1_resized.jpg](/sites/g/files/omnuum11281/files/vlsiarch/files/envm_fig1_resized.jpg) In the face of the memory wall, DRAM technology scaling issues, and ever-increasing application data demands across computing systems from the edge to the cloud, the exploration and evaluation of emerging, alternative memory technologies is an essential pursuit for enabling efficient future memory systems. We investigate, model, and evaluate the system-level implications of memory technology proposals in varying stages of development, including RRAM, STT-RAM, PCRAM, and Ferroelectric RAM. The unique physical properties of alternative, embeddable memory technologies necessitate careful co-design among memory cell characteristics, architecture design choices, and application-level optimizations. Thus, we develop and adopt a full-stack approach to modeling and evaluating systems that leverage eNVM technologies, including application-level fault tolerance analysis and analytical performance, power, and area evaluation frameworks. Additionally, we have successfully fabricated and measured the multi-level-cell programming capabilities of Charge Trap Transistors (CTTs) as an incredibly dense and entirely CMOS-compatible eNVM. Our ongoing work investigates both the design, integration, and fabrication of SoCs leveraging eNVMs and the development of comprehensive tools to facilitate design space exploration and determine the viability of eNVM proposals in different system and application contexts. ## Select Publications Download 5 citations download- [BibTeX](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=bibtex) - [EndNote X3 XML](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=endnote8) - [EndNote 7 XML](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=endnote7) - [Endnote tagged](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=tagged) - [Marc](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=marc) - [PubMedId](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=pubmed_id) - [RIS](/bibcite/export?pager_style=no_pager&number_of_items=6&sort_field=bibcite_year--desc&taxonomy_filters%5Bfield_hwp_c_peoplepublications%5D&taxonomy_filters%5Bfield_hwp_c_project123456%5D%5B0%5D%5Btarget_id%5D=172618&&&format=ris) ### 2022 L. Pentecost, A. Hankin, M. Donato, M. Hempstead, G.-Y. Wei, and D. Brooks. 2022. “[NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories](/publications/nvmexplorer-framework-cross-stack-comparisons-embedded-non-volatile-memories)”. In 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). Seoul, South Korea L. Pentecost, A. Hankin, M. Donato, M. Hempstead, G.-Y. Wei, and D. Brooks. 2022. “[NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories](/publications/nvmexplorer-framework-cross-stack-comparisons-embedded-non-volatile-memories)”. In 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). Seoul, South Korea - add\_circle\_outline do\_not\_disturb\_on Abstract - [ descriptionPublisher's Version](https://doi.org/10.48550/arXiv.2109.01188) - [ picture\_as\_pdf2109.01188.pdf](/sites/g/files/omnuum11281/files/vlsiarch/files/2109.01188.pdf) Repeated off-chip memory accesses to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy... - [ descriptionPublisher's Version](https://doi.org/10.48550/arXiv.2109.01188) - [ picture\_as\_pdf2109.01188.pdf](/sites/g/files/omnuum11281/files/vlsiarch/files/2109.01188.pdf) ### 2021 M. M. Sharifi, L. Pentecost, R. Rajaei, A. Kazemi, Q. Lou, G.-Y. Wei, D. Brooks, K. Ni, X. S. Hu, M. Niemier, and M. Donato. 2021. “[Application-Driven Design Exploration for Dense Ferroelectric Embedded Non-Volatile Memories](/publications/application-driven-design-exploration-dense-ferroelectric-embedded-non)” M. M. Sharifi, L. Pentecost, R. Rajaei, A. Kazemi, Q. Lou, G.-Y. Wei, D. Brooks, K. Ni, X. S. Hu, M. Niemier, and M. Donato. 2021. “[Application-Driven Design Exploration for Dense Ferroelectric Embedded Non-Volatile Memories](/publications/application-driven-design-exploration-dense-ferroelectric-embedded-non)” - add\_circle\_outline do\_not\_disturb\_on Abstract - [ descriptionPublisher's Version](https://doi.org/10.1109/ISLPED52811.2021.9502489) - [ picture\_as\_pdfApplication-driven Design...](/sites/g/files/omnuum11281/files/vlsiarch/files/islped52811.2021.9502489.pdf) The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell... - [ descriptionPublisher's Version](https://doi.org/10.1109/ISLPED52811.2021.9502489) - [ picture\_as\_pdfApplication-driven Design...](/sites/g/files/omnuum11281/files/vlsiarch/files/islped52811.2021.9502489.pdf) ### 2019 Lillian Pentecost, Marco Donato, Brandon Reagen, Udit Gupta, Siming Ma, Gu Wei, and David Brooks. 2019. “[MaxNVM: Maximizing DNN Storage Density and Inference Efficiency With Sparse Encoding and Error Mitigation](/publications/maxnvm-maximizing-dnn-storage-density-and-inference-efficiency-sparse-encoding)”. In MICRO ’52: Proceedings of the 52nd Annual IEEE ACM International Symposium on Microarchitecture, Pp. 769–781 Lillian Pentecost, Marco Donato, Brandon Reagen, Udit Gupta, Siming Ma, Gu Wei, and David Brooks. 2019. “[MaxNVM: Maximizing DNN Storage Density and Inference Efficiency With Sparse Encoding and Error Mitigation](/publications/maxnvm-maximizing-dnn-storage-density-and-inference-efficiency-sparse-encoding)”. In MICRO ’52: Proceedings of the 52nd Annual IEEE ACM International Symposium on Microarchitecture, Pp. 769–781 - add\_circle\_outline do\_not\_disturb\_on Abstract - [ descriptionPublisher's Version](https://doi.org/10.1145/3352460.3358258) - [ picture\_as\_pdfMaxNVM: Maximizing DNN St...](/sites/g/files/omnuum11281/files/vlsiarch/files/3352460.3358258.pdf) Deeply embedded applications require low-power, low-cost hardware that fits within stringent area constraints. Deep learning has many potential uses in these domains, but introduces significant inefficiencies stemming from off-chip DRAM accesses of model... - [ descriptionPublisher's Version](https://doi.org/10.1145/3352460.3358258) - [ picture\_as\_pdfMaxNVM: Maximizing DNN St...](/sites/g/files/omnuum11281/files/vlsiarch/files/3352460.3358258.pdf) Marco Donato, Lillian Pentecost, David Brooks, and Gu Wei. 2019. “[MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge](/publications/memti-optimizing-chip-nonvolatile-storage-visual-multitask-inference-edge)”. IEEE MICRO, 39, 6 Marco Donato, Lillian Pentecost, David Brooks, and Gu Wei. 2019. “[MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge](/publications/memti-optimizing-chip-nonvolatile-storage-visual-multitask-inference-edge)”. IEEE MICRO, 39, 6 - add\_circle\_outline do\_not\_disturb\_on Abstract - [ descriptionPublisher's Version](https://ieeexplore.ieee.org/document/8859219) - [ picture\_as\_pdfMEMTI: Optimizing On-Chip...](/sites/g/files/omnuum11281/files/vlsiarch/files/memti_optimizing_on-chip_nonvolatile_storage_for_visual_multitask_inference_at_the_edge.pdf) The combination of specialized hardware and embedded nonvolatile memories (eNVM) holds promise for energy-efficient deep neural network (DNN) inference at the edge. However, integrating DNN hardware accelerators with eNVMs still presents several... - [ descriptionPublisher's Version](https://ieeexplore.ieee.org/document/8859219) - [ picture\_as\_pdfMEMTI: Optimizing On-Chip...](/sites/g/files/omnuum11281/files/vlsiarch/files/memti_optimizing_on-chip_nonvolatile_storage_for_visual_multitask_inference_at_the_edge.pdf) ### 2018 Marco Donato, Brandon Reagen, Lillian Pentecost, Udit Gupta, David Brooks, and Gu Wei. 2018. “[On-Chip Deep Neural Network Storage With Multi-Level ENVM](/publications/chip-deep-neural-network-storage-multi-level-envm)”. In Design Automation Conference (DAC) Marco Donato, Brandon Reagen, Lillian Pentecost, Udit Gupta, David Brooks, and Gu Wei. 2018. “[On-Chip Deep Neural Network Storage With Multi-Level ENVM](/publications/chip-deep-neural-network-storage-multi-level-envm)”. In Design Automation Conference (DAC) - add\_circle\_outline do\_not\_disturb\_on Abstract - [ descriptionPublisher's Version](https://doi.org/10.1109/DAC.2018.8465818) - [ picture\_as\_pdfOn-Chip Deep Neural Netwo...](/sites/g/files/omnuum11281/files/vlsiarch/files/on-chip_deep_neural_network_storage_with_multi-level_envm.pdf) One of the biggest performance bottlenecks of today’s neural network (NN) accelerators is off-chip memory accesses. In this paper, we propose a method to use multi-level, embedded non-volatile memory (eNVM) to eliminate all off-chip weight accesses. The... - [ descriptionPublisher's Version](https://doi.org/10.1109/DAC.2018.8465818) - [ picture\_as\_pdfOn-Chip Deep Neural Netwo...](/sites/g/files/omnuum11281/files/vlsiarch/files/on-chip_deep_neural_network_storage_with_multi-level_envm.pdf) [ See all project publications arrow\_circle\_right ](https://prod-vlsiarch.drupalsites.harvard.edu/publications?f%5B0%5D=bibcite_reference_hwp_c_project123456%3A172618)