Past Projects

HELIX

The HELIX project is an automatic parallelization framework. It consists of four major components:

HELIX, a parallelizing compiler that uncovers parallelism among loop iterations.
ILDJIT, a compilation framework using a high-level intermediate representation for easy code analyses and transformations.
RingCache, a lightweight microarchitectural enhancement that enables fast core to core communication of machine words.
XIOSim, a multicore x86 performance simulator that models in-order and out-of-order cores with RingCache.

To learn more, please visit the HELIX page here.

Alarm-Based Computing

Reliable and efficient power delivery is critical to all types of computing systems. As designers seek to reduce the power consumption of systems by reducing the supply voltage, systems will begin to experience power supply fluctuations due to the finite impedance of the power supply network. These supply fluctuations, referred to as voltage emergencies, must be managed by the system to provide correctness. Our research seeks ways to handle these alarm conditions through a combined hardware/software approach. In addition to handling these alarm conditions, we consider the problem of voltage selection for power management. Energy-constrained systems typically will employ dynamic voltage and frequency scaling to match workload behavior to required performance levels – setting the voltage/frequency to the correct level to match performance needs provides the best energy efficiency. The advent of on-chip voltage regulators — which our research shows has the potential to provide fast voltage transition times and per-core voltage control — will greatly change the space of potential opportunities to apply DVFS. Our research explores these issues from a hardware/software perspective in the context of future multicore high-performance and embedded systems.

Publications

    • Wonyoung Kim, David M Brooks, Gu-Yeon Wei (2011): A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 268–270, IEEE 2011.
    • Vijay Janapa Reddi, David Brooks (2011): Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations. In: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30 (10), pp. 1429–1445, 2011.
    • Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D Smith, Gu-Yeon Wei, David Brooks (2011): Voltage Noise in Production Processors. In: IEEE Micro, 2011.
    • Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D Smith, Gu-Yeon Wei, David Brooks (2010): Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling. In: International Symposium on Microarchitecture (MICRO), IEEE 2010.
    • Vijay Janapa Reddi, Simone Campanoni, Meeta S Gupta, Michael D Smith, Gu-Yeon Wei, David Brooks, Kim Hazelwood (2010): Eliminating voltage emergencies via software-guided code transformations. In: Transactions on Architecture and Code Optimization (TACO), 2010.
    • Vijay Janapa Reddi, Meeta Gupta, Glenn Holloway, Michael D Smith, Gu-Yeon Wei, David Brooks (2010): Predicting voltage droops using recurring program and microarchitectural event activity. In: IEEE Micro, 2010.
    • And many more…

Ultra Low-Power Computing for Wireless Sensor Networks

Wireless sensor networks are an emerging computing domain that promises to deeply impact the way computers and humans interact with our environment.  Applications range from long-term environmental and seismic monitoring, vehicle tracking, health-care, and business supply-chain management.  Given the lifetime, cost, and form-factor requirements for wireless sensor nodes, energy is usually the most important design constraint.  In this project, we seek to look beyond the capabilities of general-purpose commodity microcontrollers in order to reduce energy requirements by at least an order of magnitude.  In this context, we are developing architectures that are customized for the needs of wireless sensor networks and building prototypes of these architectures.

Publications

    • Mark Hempstead, Gu-Yeon Wei, David Brooks (2008): System design considerations for sensor network applications. In: Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, pp. 2566–2569, IEEE 2008.
    • Mark Hempstead, Michael J Lyons, David Brooks, Gu-Yeon Wei (2008): Survey of hardware systems for wireless sensor networks. In: Journal of Low Power Electronics, 4 (1), pp. 11–20, 2008.
    • Mark Hempstead, David Brooks, G Wei (2011): An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS. In: Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, 1 (2), pp. 193–202, 2011.
    • Michael Lyons, David Brooks (2008): Application-Specific Hardware Design for Wireless Sensor Network Energy and Delay Reduction. In: Workshop on Optimizations for DSP and Embedded Systems (ODES), 2008.
    • Mark Hempstead, Matt Welsh, David Brooks (2004): TinyBench: The case for a standardized benchmark suite for TinyOS based wireless sensor network devices. In: Local Computer Networks, 2004. 29th Annual IEEE International Conference on, pp. 585–586, IEEE 2004.

Accelerator Store

Hardware acceleration can increase performance and reduce energy consumption. To maximize these benefits, accelerator- based systems that emphasize computation on accelerators (rather than on general purpose cores) should be used. We introduce the “accelerator store,” a structure for sharing memory between accelerators in these accelerator-based systems. The accelerator store simplifies accelerator I/O and reduces area by mapping memory to accelerators when needed at runtime. Preliminary results demonstrate a 30% system area reduction with no energy overhead and less than 1% performance overhead in contrast to conventional DMA schemes.

Publications

    • Michael Lyons, Gu-Yeon Wei, David Brooks (2012): Shrink-Fit: A Framework for Flexible Accelerator Sizing. In: Computer Architecture Letters, 2012.
    • Michael J Lyons, Mark Hempstead, Gu-Yeon Wei, David Brooks (2012): The Accelerator Store: a shared memory framework for accelerator-based systems. In: Transactions on Architecture and Code Optimization (TACO), 2012.
    • Michael Lyons, Mark Hempstead, Gu-Yeon Wei, David Brooks (2010): The Accelerator Store framework for high-performance, low-power accelerator-based systems. In: Computer Architecture Letters (CAL), 2010.

Architectural Modeling and Design with Technology Constraints

Exploring new architectures and software techniques that are aware of energy, temperature, and other lower-level design metrics is extremely important when designing modern computer systems.  New emphasis on computer systems that optimize design metrics besides raw performance, such as battery life, form-factor, and cost-efficiency provide many new challenges for system designers.  As the underlying technology continues to evolve, new design issues arise and existing challenges become more difficult.  Architectures that are aware of these issues can provide superior overall solutions. 

Publications

    • Benjamin C Lee, David Brooks (2010): Applied inference: Case studies in microarchitectural design. In: ACM Transactions on Architecture and Code Optimization (TACO), 7 (2), pp. 8, 2010.
    • Benjamin C Lee, Jamison Collins, Hong Wang, David Brooks (2008): CPR: Composable performance regression for scalable multiprocessor models. In: Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on, pp. 270–281, IEEE 2008.
    • Benjamin C Lee, David Brooks (2008): Roughness of microarchitectural design topologies and its implications for optimization. In: High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on, pp. 240–251, IEEE 2008.
    • Benjamin C Lee, David M Brooks (2007): Statistical inference for efficient microarchitectural analysis. In: 2007.
    • Benjamin C Lee, David M Brooks (2006): Accurate and efficient regression modeling for microarchitectural performance and power prediction. In: ACM SIGOPS Operating Systems Review, pp. 185–194, ACM 2006.
    • And many more…

Multi-Layer Efforts to Mitigate Process Variations

Exploring new architectures and software techniques that are aware of energy, temperature, and other lower-level design metrics is extremely important when designing modern computer systems.  New emphasis on computer systems that optimize design metrics besides raw performance, such as battery life, form-factor, and cost-efficiency provide many new challenges for system designers.  As the underlying technology continues to evolve, new design issues arise and existing challenges become more difficult.  Architectures that are aware of these issues can provide superior overall solutions. 

Publications

    • Xiaoyao Liang, Gu-Yeon Wei, David Brooks (2008): Revival: A variation-tolerant architecture using voltage interpolation and variable latency. In: Computer Architecture, 2008. ISCA'08. 35th International Symposium on, pp. 191–202, IEEE 2008.
    • Meeta S Gupta, Jude A Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks (2009): Tribeca: design for PVT variations with local recovery and fine-grained adaptation. In: Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pp. 435–446, IEEE 2009.
    • Xiaoyao Liang, David Brooks, Gu-Yeon Wei (2008): A process-variation-tolerant floating-point unit with voltage interpolation and variable latency. In: Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 404–623, IEEE 2008.
    • Kevin Brownell, Gu-Yeon Wei, David Brooks (2008): Evaluation of voltage interpolation to address process variations. In: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 529–536, IEEE Press 2008.
    • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks (2007): Process variation tolerant 3T1D-based cache architectures. In: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 15–26, IEEE Computer Society 2007.
    • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M Brooks (2007): Process Variation Tolerant Register Files Based On Dynamic Memories. In: Workshop on Architectural Support for Gigascale Integration, held with Int’l Symposium on Computer Architecture (ISCA-34), 2007.
    • And many more…