An adaptive issue queue for reduced power at high performance Journal Article
Power-Aware Computer Systems, pp. 25–39, 2001.
A circuit level implementation of an adaptive issue queue for power-aware microprocessors Inproceedings
Proceedings of the 11th Great Lakes symposium on VLSI, pp. 73–78, ACM 2001.
Power-performance modeling and tradeoff analysis for a high end microprocessor Journal Article
Power-Aware Computer Systems, pp. 126–136, 2001.
Modeling and analyzing CPU power and performance: Metrics, methods, and abstractions Journal Article
SIGMETRICS 2001/Performance 2001-Tutorials, 2001.
Live, runtime power measurements as a foundation for evaluating power/performance tradeoffs Journal Article
Workshop on Complexity Effectice Design WCED, held in conjunction with ISCA, 28 , 2001.
Modeling and Analyzing CPU Power and Performance: Metrics, Methods, and Abstractions Journal Article
Tutorial, ACM SIGMETRICS, 2001.
Design and modeling of power-efficient computer architectures Journal Article
Wattch: a framework for architectural-level power analysis and optimizations Inproceedings
ACM SIGARCH Computer Architecture News, pp. 83–94, ACM 2000.
Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors Journal Article
Micro, IEEE, 20 (6), pp. 26–44, 2000.
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance Journal Article
ACM Transactions on Computer Systems (TOCS), 18 (2), pp. 89–126, 2000.
Adaptive thermal management for high-performance microprocessors Inproceedings
In Workshop on Complexity Effective Design, Citeseer 2000.
Wattch: A framework for architectural-level power analysis and optimizations Journal Article
isca, pp. 83, 2000.
Dynamically exploiting narrow width operands to improve processor power and performance Inproceedings
High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On, pp. 13–22, IEEE 1999.
Implementing application-specific cache-coherence protocols in configurable hardware Journal Article
Network-Based Parallel Computing. Communication, Architecture, and Applications, pp. 181–195, 1999.
Power-Aware Architecture Studies: Omgoing Work at Princeton Journal Article
Power-Driven Microarchitecture Workshop, 1998.
Combating process variations Journal Article
Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations Journal Article
Voltage emergency prediction Journal Article
Power-Performance and Power Swing Characterization in Adaptive Microarchitectures Journal Article
Power, Performance and Portability: System Design Considerations for Micro Air Vehicle Applications Journal Article
Workshop on Near-threshold Computing (WNTC) Journal Article