Haley Family Professor of Computer Science
Dr. Brooks received his B.S. from University of Southern California in EE in 1997 and his M.A. and Ph.D. in EE from Princeton in 2001. He spent a year at IBM T.J. Watson Research Center in 2001 before joining Harvard in 2002. His research focuses on the interaction between the architecture and software of computer systems and underlying hardware implementation challenges, including power, reliability, and variability issues across embedded and high-performance computing systems.
Gordon McKay Professor of Electrical Engineering
Dr. Wei received his B.S.E.E., M.S., and Ph.D. in Electrical Engineering from Stanford University in 1994, 1997, and 2001, respectively. In 2000, he joined Accelerant Networks (now a part of Synopsys) in Beaverton, Oregon as a Senior Design Engineer. In 2002, he joined Harvard University. His research interests span a variety of topics such as integrated voltage regulators, flexible voltage stacking, power electronics, low-power computing architectures and circuits, auto-parallelizing compilers, and more.
Dr. Donato received his B.S. and M.S. (cum laude) in Electrical Engineering from the University of Rome “La Sapienza”, Italy, in 2008 and 2010, respectively, and his Ph.D. in Electrical Sciences and Computer Engineering from Brown University in 2016. In 2017, he joined Harvard University. His research interests include modeling and analysis of noise sources in nanoscale circuits, and automated tools for noise-tolerant circuit architectures. He is currently working on the design of novel embedded memory subsystems and circuitry in advanced CMOS technology nodes with applications to machine learning hardware accelerator SoCs.
Dr. Ko received his B.S. in Electrical Engineering as a James Scholar in three years with minors in Mathematics and Computer Science, and M.S. in Electrical and Computer Engineering, from University of Illinois at Urbana-Champaign. In 2007, he joined Samsung Electronics where he engaged in research and development of Samsung Exynos mobile processors. In 2011, he returned to University of Illinois at Urbana-Champaign and received his Ph.D. in Electrical and Computer Engineering. His current research interests include machine learning algorithms and hardware accelerators.
Yuan received his B.S. in Computer Science from Zhejiang University. He received his Ph.D. from the same university in 2017, during which he spent three years at National University of Singapore as a research intern. His current research interests include hardware accelerators and cache hierarchies.
Current Graduate Students
Bob studies modeling, analysis, and optimization techniques for high-performance software, with a current focus on deep learning. His philosophy is that the combination of statistical methods, code analysis, and domain knowledge leads to better tools for understanding and building fast systems. Bob earned his B.S. at Northwestern in 2005, spent four years writing performance analysis tools for supercomputers at the DoD, and another three years at PNNL leading research in massively multithreaded architectures and high-performance graph analysis.
Simon received a B.Eng. and M.Sc.A. in Electrical Engineering from Université de Sherbrooke, Canada and worked at Teledyne DALSA. His research interests include analog and mixed-signal design and power electronics. More specifically, he is interested in finding new ways to integrate heterogeneous technology at a system level. For instance, design new power converter topology to enable the integration of MEMS actuators in portable applications, thus enabling new functions for these devices.
Thomas (Hsea-Ching) Hsueh
Thomas received his Bachelors degree in Electrical Engineering from National Taiwan University in 2015. His current research interest includes hardware accelerator, energy-efficient architecture, machine learning and cognitive neuroscience.
Lillie received her B.A. in Physics and Computer Science from Colgate University in 2016. Her general research interests are in computer architecture, specialized hardware, and software-hardware co-design, and some of her previous work includes hardware support for dynamically typed languages, simulation and data analysis tools for particle accelerator performance, and fundamental physics experiments with superconducting electronics.
Thierry received his B.S (2010) and M.Eng (2012) in Electrical Engineering from Texas A&M University with a focus on analog/mixed-signal VLSI. He spent five years at Intel designing various circuitries for high-bandwidth memory and peripheral interfaces on HPC SoCs. His current research interests include hardware accelerators for deep learning and agile SoC design methodologies.
Yu (Emma) Wang
My research focuses on full-stack system design for machine learning workloads, from hardware platforms, to software stacks and applications. Benchmarking is crucial to understand workload characteristics, reveal computational bottlenecks, and provide optimization opportunities. I have been working on deep learning and Bayesian inference workloads, by benchmarking them on real systems including CPU, GPU, TPU, highlighting the system bottlenecks, and providing insights on future machine learning system design. I also research on the performance impact of software stacks including frameworks and machine learning libraries. I received my B.S in Computer Science from Shanghai Jiao Tong University in 2013.
I am a Ph.D. student working on hardware-software co-design of systems software. I graduated in 2016 from Northeastern University with a Bachelors in Electrical and Computer Engineering. My past experience has been mostly in computer architecture and microprocessor reliability. I worked for a number of years while on co-op at AMD Research in reliability as well as in the Northeastern Computer Architecture lab (NUCAR) with David Kaeli. In my spare time I enjoy practicing martial arts and yoga, as well as playing video games.
“Advancing System-Level Analysis and Design of Specialized Architectures”
Software Engineer, Google
“On the Design and Optimization of Specialized Hardware with Applications in Deep Learning”
Research Scientist, Facebook
Mario Lok, Ph.D. 2016
“Power Electronics Design for an Insect Scale, Flapping Wing Robot Using High Voltage Integrated Circuits”
Hardware Engineer, Apple.
Sae Kyu Lee, Ph.D. 2016
“High Efficiency Power Delivery for Chip Multiprocessors Using Voltage Stacking”
Postdoctoral Fellow, Harvard.
Svilen Kanev, Ph.D. 2016
“Efficiency in warehouse-scale computers: a datacenter tax study”
Software Engineer, Google.
Hyunkwang Lee, M.S. 2016
Yakun Sophia Shao, Ph.D. 2016
“Design and Modeling of Specialized Architectures”
Research Scientist, NVIDIA.
Kevin Brownell, Ph.D. 2015
“Architectural Implications of Automatic Parallelization with HELIX-RC”
Software Engineer, Google.
Tao Tong, Ph.D. 2015
“Improving SoC power delivery with fully integrated voltage regulators”
Michael Lyons, Ph.D. 2013.
“Toward a hardware accelerated future”
Software Engineer, Dropbox.
Wonyoung Kim, Ph.D. 2013
“Reducing power loss, cost and complexity of soc power delivery using integrated 3-level voltage regulators”
Founder and CEO, Lion Semiconductor.
Judson Porter, M.S. 2012
Software Engineer, Google Inc.
Michael Karpelson, Ph.D. 2012.
“Power electronics design for a flapping-wing robotic insect”
Krishna Rangan, Ph.D. 2011.
“Hardware-based thread scheduling for power-efficient and variation-resilient chip multiprocessors”
Ankur Agrawal, Ph.D. 2010.
“Design of high speed I/O interfaces for high performance microprocessors”
Research Staff, IBM Research.
Vijay Janapa Reddi, Ph.D. 2010.
“Software-assisted hardware reliability: Using runtime feedback from hardware and software to enable aggressive timing speculation”
Assistant Professor, University of Texas, Austin.
Meeta Gupta, Ph.D. 2009.
“Variation-aware processor architectures with aggressive operating margins”
Researcher, IBM India Research Labs.
Mark Hempstead, Ph.D. 2009.
“Accelerator-based architectures for wireless sensor network applications”
Assistant Professor, Drexel University.
Benjamin Lee, Ph.D. 2008.
“Statistical inference for efficient microarchitectural analysis”
Assistant Professor, Ph.D. Duke University.
Xiaoyao Liang, Ph.D. 2008.
“From uncertainty to opportunity: Joint architecture and circuit resilience to mitigate the impact of process variations”
Professor, Shanghai Jiaotong University.