Chip Gallery

Chip prototyping provides several important benefits for our research. Silicon implementation provides the opportunity to learn about power and variability issues with real measurements in ways that simulations alone cannot provide, and our chip prototypes allow us to more convincingly demonstrate the benefits of our proposed approaches. In addition, the design process instills an appreciation of complexity, testing, and validation issues encountered when creating real hardware. Our group has designed prototype chips for several projects.

We thank IBM, TSMC, SRC, and UMC for fabrication support for these projects.

 

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A 16-Core Voltage-Stacked System with an Integrated Switched-Capacitor DC-DC Converter Sae Kyu Lee, Tao Tong, Xuang Zhang, David Brooks, Gu-Yeon Wei. IEEE Symposium on VLSI Circuits (VLSIC), 2015. A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications.

Tong, Tao and Lee, Sae Kyu and Zhang, Xuan and Brooks, David and Wei, Gu-Yeon
IEEE Journal of Solid-State Circuits, vol. 51, no. 9, 2016

An integrated 300Volts drive stage for piezoelectric actuators used in micro-robotic systems. Design and analysis of an integrated driver for piezoelectric actuators Lok, M.; Brooks, D.; Wood, R.; Gu-Yeon Wei Energy Conversion Congress and Exposition (ECCE), 2013 IEEE , vol., no., pp.2684,2691, 15-19 Sept. 2013

 

An integrated 300Volts drive stage for piezoelectric actuators used in micro-robotic systems.
Design and analysis of an integrated driver for piezoelectric actuators
Lok, M.; Brooks, D.; Wood, R.; Gu-Yeon Wei
Energy Conversion Congress and Exposition (ECCE), 2013 IEEE , vol., no., pp.2684,2691, 15-19 Sept. 2013

 

 

Wireless sensor network test chip, ULP-1, .18um IBM CMOS. 1st Prize in SRC SoC Design Contest. Implementation of our architecture that appears in Hempstead et al, ISCA 2005.

Voltage Interpolation/Variable Latency FPU test chip, .13um UMC CMOS. Measurement results appear in Liang et al, ISSCC 2008 and provides a companion to our ISCA 2008 architectural study.

 

Voltage Interpolation/Variable Latency FPU test chip, .13um UMC CMOS.

Measurement results appear in Liang et al, ISSCC 2008 and provides a companion to our ISCA 2008 architectural studies.

A three level DC-DC converter that demonstrates fast voltage scaling (on the order of nanoseconds) for fast DVFS. Implemented in UMC 130nm CMOS. A fully-integrated 3-level DC-DC converter for nanosecond-scale DVFS Kim, Wonyoung; Brooks, David; Wei, Gu-Yeon Solid-State Circuits, IEEE Journal of, 47 (1), pp. 206–219, 2012.

 

A three level DC-DC converter that demonstrates fast voltage scaling (on the order of nanoseconds) for fast DVFS. Implemented in UMC 130nm CMOS.
A fully-integrated 3-level DC-DC converter for nanosecond-scale DVFS
Kim, Wonyoung; Brooks, David; Wei, Gu-Yeon
Solid-State Circuits, IEEE Journal of, 47 (1), pp. 206–219, 2012.

Prototype near-threshold voltage stacking test-chip comprising of 3x3 array of power-consuming cores fabricated in MIT Lincoln Lab's 150nm near-threshold optimized fully-depleted SOI (FDSOI) process. Evaluation of Voltage Stacking for Near-Threshold Multicore Computing S. Lee, D. Brooks, and G. Wei International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2012, Redondo Beach, CA, USA

 

Prototype near-threshold voltage stacking test-chip comprising of 3×3 array of power-consuming cores fabricated in MIT Lincoln Lab’s 150nm near-threshold optimized fully-depleted SOI (FDSOI) process.
Evaluation of Voltage Stacking for Near-Threshold Multicore Computing
S. Lee, D. Brooks, and G. Wei
International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2012, Redondo Beach, CA, USA

A Fully Integrated Battery-Connected Switched-Capacitor 4:1 Voltage Regulator with 70% Peak Efficiency Using Bottom-Plate Charge Recycling Tong, Tao; Zhang, Xuan; Kim, Wonyoung; Brooks, David; Wei, Gu-Yeon IEEE Custom Integrated Circuits Conference (CICC), 2013.

 

A Fully Integrated Battery-Connected Switched-Capacitor 4:1 Voltage Regulator with 70% Peak Efficiency Using Bottom-Plate Charge Recycling
Tong, Tao; Zhang, Xuan; Kim, Wonyoung; Brooks, David; Wei, Gu-Yeon
IEEE Custom Integrated Circuits Conference (CICC), 2013.

The prototype microrobotic SoC designed for the RoboBee contains a fully integrated high efficiency switched-capacitor voltage regulator, a 32-bit ARM Cortex-M0 general-purpose processor with 128 KB on-chip memories, a programmable voltage-tracking adaptive-frequency clock, and a low-power high-precision frequency reference. Supply-Noise Resilient Adaptive Clocking for Battery-Powered Aerial Microrobotic System-on-Chip in 40nm CMOS X. Zhang, T. Tong, D. Brooks, and G. Wei IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013, San Jose, USA.

 

The prototype microrobotic SoC designed for the RoboBee contains a fully integrated high efficiency switched-capacitor voltage regulator, a 32-bit ARM Cortex-M0 general-purpose processor with 128 KB on-chip memories, a programmable voltage-tracking adaptive-frequency clock, and a low-power high-precision frequency reference.

Supply-Noise Resilient Adaptive Clocking for Battery-Powered Aerial Microrobotic System-on-Chip in 40nm CMOS
X. Zhang, T. Tong, D. Brooks, and G. Wei
IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013, San Jose, USA